Adam Milik

16 papers C 4Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2018 J jnl
Multiple-Core PLC CPU Implementation and Programming.
J. Circuits Syst. Comput.
Adam Milik
2017 J jnl
Nonlinearity Measurement of a Voltage Ramp Using a Digital Technique.
J. Circuits Syst. Comput.
Adam Milik, Edward Hrynkiewicz
2016 J jnl
On hardware synthesis and implementation of PLC programs in FPGAs.
Microprocess. Microsystems
Adam Milik
2013 — conf
On Hardware Synthesis of Reconfigurable Logic Controllers from Ladder Diagrams According to IEC61131-3.
PDeS
Adam Milik
2012 — conf
Dynamic rescheduling of tasks in time predictable embedded systems.
PDeS
Andrzej Pulka, Adam Milik
2012 — conf
On mapping of DSP48 units for arithmetic operation in reconfigurable logic controllers.
PDeS
Adam Milik
2011 — conf
Automatic implementation of arithmetic operation in reconfigurable logic controllers.
ECCTD
Adam Milik, Andrzej Pulka
2010 — ed.
10th IFAC Workshop on Programmable Devices and Embedded Systems, PDeS 2010, Gliwice, Poland, October 6-7, 2010.
PDeS
Adam Milik, Edward Hrynkiewicz
2010 J jnl
Logic synthesis based on decomposition for CPLDs.
Microprocess. Microsystems
Dariusz Kania, Adam Milik
2010 — conf
On efficient implementation of search algorithm for genome patterns.
PDeS
Adam Milik, Andrzej Pulka
2009 — conf
Multithread RISC architecture based on programmable interleaved pipelining.
ICECS
Andrzej Pulka, Adam Milik
2009 — conf
The reconfigurable hardware accelerator for searching genome patterns.
PDeS
Adam Milik, Andrzej Pulka
2008 C conf
VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams.
FDL
Andrzej Pulka, Adam Milik
2007 C conf
Common HDL-Matlab Simulation Environment.
FDL
Adam Milik, Andrzej Pulka
2005 C conf
A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs.
DSD
Dariusz Kania, Józef Kulisz, Adam Milik
2005 C conf
Decomposition of Multi-Output Functions for CPLDs.
DSD
Dariusz Kania, Adam Milik, Józef Kulisz