Abir J. Mondal

18 papers Misc 1Journal 10Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 17pJ-External Oscillator Less Differential Delay Cell-Based Time-Domain Smart Temperature Sensor.
J. Circuits Syst. Comput.
Kuntal Chakraborty, Abir J. Mondal
2025 — conf
A Multi-Resolution Mode Energy and Area Efficient All Digital Smart Temperature Sensor.
ICEIC
Kuntal Chakraborty, Alak Majumder, Abir J. Mondal
2024 Misc conf
Design and Analysis of an Area and Power Efficient Programmable Delay Cell.
VLSID
Kuntal Chakraborty, Jai Gopal Pandey, Abir J. Mondal
2024 J jnl
On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ.
Integr.
Kuntal Chakraborty, Abir J. Mondal
2024 J jnl
Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient.
J. Circuits Syst. Comput.
Kuntal Chakraborty, Alak Majumder, Abir J. Mondal
2023 — conf
Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.
RADIOELEKTRONIKA
Pritam Bhattacharjee, G. Naveen Goud, Vipin Kumar Singh, Vijay Pratap Yadav, Abir J. Mondal, Alak Majumder
2022 J jnl
A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link.
Integr.
Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya
2022 J jnl
Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current.
J. Circuits Syst. Comput.
Mithilesh Kumar, Alak Majumder, Abir J. Mondal
2021 J jnl
A PVT aware differential delay circuit and its performance variation due to power supply noise.
Integr.
Anirban Tarafdar, Abir J. Mondal, Uttam Kumar Bera, Bidyut K. Bhattacharyya
2019 J jnl
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya
2017 J jnl
A 65 nm Design of 0.6 V/8.98
J. Low Power Electron.
Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
2017 — conf
A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application.
iNIS
Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
2017 — conf
A Design Methodology for MOS Current Mode Logic VCO.
iNIS
Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
2017 J jnl
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit.
Integr.
Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
2017 J jnl
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect.
Integr.
Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
2016 — conf
A constraint driven technique for MOS amplifier design.
VDAT
Paromita Bhattacharjee, Abir J. Mondal, Alak Majumder
2016 — conf
A method to design a comparator for sampled data processing applications.
VDAT
Rama Prasad Acharya, Abir J. Mondal, Alak Majumder
2015 — conf
Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs.
LATS
Sandeep Kumar Singh, Abir J. Mondal, Alak Majumder