Abinash Roy

18 papers A* 2A 1C 6Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2022 J jnl
SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rassul Bairamkulov, Abinash Roy, Mahalingam Nagarajan, Vaishnav Srinivas, Eby G. Friedman
2021 A* conf
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping.
DAC
Rassul Bairamkulov, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas, Eby G. Friedman
2020 C conf
Graph-Based Power Network Routing for Board-Level High Performance Systems.
ISCAS
Rassul Bairamkulov, Eby G. Friedman, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas
2019 — conf
Learning-based prediction of package power delivery network quality.
ASP-DAC
Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, Bangqi Xu
2010 J jnl
Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns.
IEEE Trans. Very Large Scale Integr. Syst.
Abinash Roy, Jingye Xu, Masud H. Chowdhury
2008 C conf
Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects.
ISCAS
Abinash Roy, Masud H. Chowdhury
2008 J jnl
Compound noise separation in digital circuits using blind source separation.
Microelectron. J.
Jingye Xu, Vivek Nigam, Abinash Roy, Masud H. Chowdhury
2008 — conf
Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects.
ICECS
Abinash Roy, Jingye Xu, Masud H. Chowdhury
2008 J jnl
Noise separation in analog integrated circuits using independent component analysis technique.
Integr. Comput. Aided Eng.
Jingye Xu, Abinash Roy, Masud H. Chowdhury
2008 C conf
Optimization technique for flip-flop inserted global interconnect.
ISCAS
Jingye Xu, Abinash Roy, Masud H. Chowdhury
2007 — conf
Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects.
ICECS
Abinash Roy, Sharada Jha, Masud H. Chowdhury
2007 C conf
Delay and Clock Skew Variation due to Coupling Capacitance and Inductance.
ISCAS
Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury
2007 A* conf
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew.
DAC
Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury
2007 C conf
Global Interconnect Optimization in the Presence of On-chip Inductance.
ISCAS
Abinash Roy, Masud H. Chowdhury
2007 A conf
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining.
DATE
Jingye Xu, Abinash Roy, Masud H. Chowdhury
2007 C conf
Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.
ISCAS
Jingye Xu, Abinash Roy, Masud H. Chowdhury
2007 J jnl
Power Consumption and BER of Flip-Flop Inserted Global Interconnect.
VLSI Design
Jingye Xu, Abinash Roy, Masud H. Chowdhury
2006 — conf
Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect.
APCCAS
Abinash Roy, Masud H. Chowdhury