Abinash Mohanty

16 papers A 2B 1C 2Misc 1Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2024 J jnl
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design.
ACM Trans. Reconfigurable Technol. Syst.
Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2021 B conf
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression.
FPL
Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2019 J jnl
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae-sun Seo
2019 J jnl
Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches.
CoRR
Xiaocong Du, Gokul Krishnan, Abinash Mohanty, Zheng Li, Gouranga Charan, Yu Cao
2018 — —
Algorithm and Hardware Design for Efficient Deep Learning Inference.
Abinash Mohanty
2018 Misc conf
Towards a Wearable Cough Detector Based on Neural Networks.
ICASSP
Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha
2017 — conf
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
ASP-DAC
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
2017 C conf
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
ISCAS
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
2017 J jnl
RTN in Scaled Transistors for On-Chip Random Seed Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Abinash Mohanty, Ketul B. Sutaria, Hiromitsu Awano, Takashi Sato, Yu Cao
2016 C conf
High-performance face detection with CPU-FPGA acceleration.
ISCAS
Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2016 A conf
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.
FPGA
Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2015 — conf
Duty cycle shift under static/dynamic aging in 28nm HK-MG technology.
IRPS
Ketul B. Sutaria, Pengpeng Ren, Abinash Mohanty, Xixiang Feng, Runsheng Wang, Ru Huang, Yu Cao
2015 J jnl
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2015 A conf
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
DATE
Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2014 — conf
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
BioCAS
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2014 — conf
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.
BICA
Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao