Abhishek Kumar Jain

20 papers A 2B 1C 1Misc 4Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2023 J jnl
Entropy Maximization in Sparse Matrix by Vector Multiplication (max
CoRR
Paolo D'Alberto, Abhishek Kumar Jain, Ismail Bustany, Henri Fraisse, Mansimran Benipal
2023 Misc conf
Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs.
FCCM
Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde
2022 J jnl
Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation.
IEEE Trans. Parallel Distributed Syst.
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2021 — conf
Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform.
HPEC
Abhishek Kumar Jain, Sharan Kumar, Aashish Tripathi, Dinesh Gaitonde
2020 B conf
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs.
FPL
Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde
2020 C conf
High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay.
ISCAS
Xiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain
2020 — conf
Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited).
SLIP
Abhishek Kumar Jain
2019 J jnl
Performance Assessment of Emerging Memories Through FPGA Emulation.
IEEE Micro
Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale
2018 A conf
A time-multiplexed FPGA overlay with linear interconnect.
DATE
Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2018 Misc conf
Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments.
FCCM
Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale
2017 — —
Architecture centric coarse-grained FPGA overlays
Abhishek Kumar Jain
2017 J jnl
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays.
CoRR
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2016 J jnl
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units.
CoRR
Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2016 — conf
Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?
DASC/PiCom/DataCom/CyberSciTech
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2016 Misc conf
DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect.
FCCM
Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy
2016 A conf
Throughput oriented FPGA overlays using DSP blocks.
DATE
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2015 J jnl
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq.
SIGARCH Comput. Archit. News
Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell
2015 Misc conf
Efficient Overlay Architecture Based on DSP Blocks.
FCCM
Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell
2014 J jnl
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform.
J. Signal Process. Syst.
Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell
2013 — conf
Microkernel hypervisor for a hybrid ARM-FPGA platform.
ASAP
Khoa Dang Pham, Abhishek Kumar Jain, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell