Abhishek Jain - RankMe

14 papers A 1B 1C 3Misc 1Journal 5Unranked 3

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing. IEEE J. Solid State Circuits Abhishek Jain, Andrea Mario Veggetti, Dennis Crippa, Antonio Benfante, Simone Gerardin, Marta Bagatin
2020	C	`conf`	Single Phase Clock Based Radiation Tolerant D Flip-flop Circuit. IOLTS Abhishek Jain, Andrea Veggetti, Dennis Crippa, Antonio Benfante, Simone Gerardin, Marta Bagatin
2017	A	`conf`	Cognitive approach to support dynamic aging compensation. ITC Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, David Meyer, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix
2017	C	`conf`	Dynamic aging compensation and Safety measures in Automotive environment. IOLTS Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix
2016	C	`conf`	Activity profiling: Review of different solutions to develop reliable and performant design. IOLTS Florian Cacho, Ahmed Benhassain, Souhir Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, Vincent Knopik, Abhishek Jain, C. R. Parthasarathy, Lorena Anghel
2016	J	`jnl`	Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors. VLSI Design Abhishek Jain, Richa Gupta
2015	Misc	`conf`	Scaling the UVM_REG Model towards Automation and Simplicity of Use. VLSID Abhishek Jain, Richa Gupta
2015	—	`conf`	Timing in-situ monitors: Implementation strategy and applications results. CICC Ahmed Benhassain, Florian Cacho, Vincent Huard, M. Saliva, Lorena Anghel, C. R. Parthasarathy, Abhishek Jain, Fabien Giner
2014	J	`jnl`	Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator. CoRR Abhishek Jain, Piyush Kumar Gupta, Hima Gupta, Sachish Dhar
2014	J	`jnl`	Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL. CoRR Abhishek Jain, Hima Gupta, Sandeep Jana, Krishna Kumar
2013	J	`jnl`	Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs CoRR Abhishek Jain, Giuseppe Bonanno, Hima Gupta, Ajay Goyal
2012	B	`conf`	On-chip delay measurement circuit. ETS Abhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi
2010	—	`conf`	An On-Chip Flip-Flop Characterization Circuit. PATMOS Abhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi
2008	—	`conf`	A novel approach to video matting using automated scribbling by motion analysis. VECIMS Abhishek Jain, Madhur Agrawal, Abhinav Gupta, Vineet Khandelwal