Abhijit R. Asati

20 papers Journal 15Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	FPGA-Based Implementation of Single-Cycle High-Throughput LDPC Encoder for 5G New Radio. IEEE Embed. Syst. Lett. A. Sharma, Gaurav Purohit, Abhijit R. Asati
2022	J	`jnl`	Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis. Wirel. Pers. Commun. Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
2022	J	`jnl`	Dedicated hardware architecture for localizing iris in VW images. J. King Saud Univ. Comput. Inf. Sci. Vineet Kumar, Abhijit R. Asati, Anu Gupta
2021	J	`jnl`	High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications. Comput. Intell. Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
2021	J	`jnl`	Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications. Circuits Syst. Signal Process. Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
2021	J	`jnl`	Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm. Microprocess. Microsystems Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
2020	J	`jnl`	High-Level synthesis assisted design and verification framework for automotive radar processors. Microprocess. Microsystems Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
2020	J	`jnl`	Speed optimal FPGA implementation of the encryption algorithms for telecom applications. Microprocess. Microsystems Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
2018	J	`jnl`	Hardware Accelerators for Iris Localization. J. Signal Process. Syst. Vineet Kumar, Abhijit R. Asati, Anu Gupta
2018	J	`jnl`	Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation. IET Image Process. Vineet Kumar, Abhijit R. Asati, Anu Gupta
2017	J	`jnl`	Low-latency median filter core for hardware implementation of 5 × 5 median filtering. IET Image Process. Vineet Kumar, Abhijit R. Asati, Anu Gupta
2016	J	`jnl`	A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images. J. Electr. Comput. Eng. Vineet Kumar, Abhijit R. Asati, Anu Gupta
2015	—	`conf`	An Iris localization method for noisy infrared iris images. ICSIPA Vineet Kumar, Abhijit R. Asati, Anu Gupta
2015	J	`jnl`	Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region. Int. J. Reconfigurable Comput. Priya Gupta, Anu Gupta, Abhijit R. Asati
2014	—	`conf`	Iris based biometric identification system. ICAILP Ankur Kumar, Abhijit R. Asati
2012	—	`conf`	Design of a Static Current Simulator Using Device Matrix Approach. ISED Deepak Bharti, Abhijit R. Asati
2010	J	`jnl`	A Novel Redundant Binary Number to Natural Binary Number Converter. J. Signal Process. Syst. Subhendu Kumar Sahoo, Anu Gupta, Abhijit R. Asati, Chandra Shekhar
2009	J	`jnl`	Dual channel addition based FFT processor architecture for signal and image processing. Int. J. High Perform. Syst. Archit. Subhendu Kumar Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati, Anu Gupta
2009	—	`conf`	Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load. ICETET Abhijit R. Asati, Subhendu Kumar Sahoo, Chandra Shekhar
2008	—	`conf`	An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style. ICIIS Abhijit R. Asati, Chandrashekhar