Abhijit Jas

34 papers A 4B 2C 2Misc 5Journal 12Unranked 9
YearRankTypeTitle / Venue / Authors
2013 J jnl
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.
J. Electron. Test.
Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche
2012 J jnl
Functional Test-Sequence Grading at Register-Transfer Level.
IEEE Trans. Very Large Scale Integr. Syst.
Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
2011 B conf
AVF Analysis Acceleration via Hierarchical Fault Pruning.
ETS
Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
2011 J jnl
Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.
IEEE Trans. Computers
Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
2011 J jnl
Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.
IEEE Trans. Computers
Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris
2010 — conf
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.
Conf. Computing Frontiers
Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche
2010 J jnl
Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou
2009 J jnl
FPGA-based hardware acceleration for Boolean satisfiability.
ACM Trans. Design Autom. Electr. Syst.
Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas
2009 C conf
Impact analysis of performance faults in modern microprocessors.
ICCD
Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
2009 Misc conf
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller.
VTS
Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
2009 Misc conf
RT-Level Deviation-Based Grading of Functional Test Sequences.
VTS
Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
2008 J jnl
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs.
J. Electron. Test.
Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty
2008 A conf
A low-cost concurrent error detection technique for processor control logic.
DATE
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche
2008 — conf
Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes.
ISQED
Avijit Dutta, Abhijit Jas
2008 — conf
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.
DFT
Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti
2008 B conf
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.
ETS
Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche
2008 A conf
On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors.
ITC
Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris
2008 — conf
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering.
ASP-DAC
Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou
2007 — conf
Analysis of Specified Bit Handling Capability of Combinational Expander Networks.
DFT
Abhijit Jas, Srinivas Patil
2007 — conf
The Region-Exhaustive Fault Model.
ATS
Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil
2006 — conf
An Approach to Minimizing Functional Constraints.
DFT
Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty
2004 J jnl
Achieving high encoding efficiency with partial dynamic LFSR reseeding.
ACM Trans. Design Autom. Electr. Syst.
C. V. Krishna, Abhijit Jas, Nur A. Touba
2004 J jnl
Test data compression technique for embedded cores using virtual scan chains.
IEEE Trans. Very Large Scale Integr. Syst.
Abhijit Jas, Bahram Pouya, Nur A. Touba
2004 J jnl
Weighted pseudorandom hybrid BIST.
IEEE Trans. Very Large Scale Integr. Syst.
Abhijit Jas, C. V. Krishna, Nur A. Touba
2003 J jnl
An efficient test vector compression scheme using selective Huffman coding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba
2002 J jnl
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor.
J. Electron. Test.
Abhijit Jas, Nur A. Touba
2001 Misc conf
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme.
VTS
Abhijit Jas, C. V. Krishna, Nur A. Touba
2001 A conf
Test vector encoding using partial LFSR reseeding.
ITC
C. V. Krishna, Abhijit Jas, Nur A. Touba
2000 Misc conf
Virtual Scan Chains: A Means for Reducing Scan Length in Cores.
VTS
Abhijit Jas, Bahram Pouya, Nur A. Touba
1999 — conf
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets.
Asian Test Symposium
Abhijit Jas, Kartik Mohanram, Nur A. Touba
1999 — conf
Configuration self-test in FPGA-based reconfigurable systems.
ISCAS (1)
W. Quddus, Abhijit Jas, Nur A. Touba
1999 Misc conf
Scan Vector Compression/Decompression Using Statistical Coding.
VTS
Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba
1999 C conf
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip.
ICCD
Abhijit Jas, Nur A. Touba
1998 A conf
Test vector decompression via cyclical scan chains and its application to testing core-based designs.
ITC
Abhijit Jas, Nur A. Touba