Abhijit Ghosh - RankMe

39 papers A* 4A 10C 3Misc 2Journal 15Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Natural language processing to identify suicidal ideation and anhedonia in major depressive disorder. BMC Medical Informatics Decis. Mak. L. Alexander Vance, Leslie Way, Deepali Kulkarni, Emily O. C. Palmer, Abhijit Ghosh, Melissa Unruh, Kelly M. Y. Chan, Amey Girdhari, Joydeep Sarkar
2024	A*	`conf`	A Plentoptic 3D Vision System. SIGGRAPH Asia Agastya Kalra, Vage Taamazyan, Alberto Dall'olio, Raghav Khanna, Tomas Gerlich, Georgia Giannopolou, Guy Stoppi, Daniel Baxter, Abhijit Ghosh, Richard Szeliski, Kartik Venkataraman
2024	J	`jnl`	Enhancing pre-trained contextual embeddings with triplet loss as an effective fine-tuning method for extracting clinical features from electronic health record derived mental health clinical notes. Nat. Lang. Process. J. Deepali Kulkarni, Abhijit Ghosh, Amey Girdhari, Shaomin Liu, L. Alexander Vance, Melissa Unruh, Joydeep Sarkar
2023	J	`jnl`	Neural Shading Fields for Efficient Facial Inverse Rendering. Comput. Graph. Forum Gilles Rainer, Lewis Bridgeman, Abhijit Ghosh
2022	J	`jnl`	High-performance computation of pricing two-asset American options under the Merton jump-diffusion model on a GPU. Comput. Math. Appl. Abhijit Ghosh, Chittaranjan Mishra
2021	J	`jnl`	A Parallel Cyclic Reduction Algorithm for Pentadiagonal Systems with Application to a Convection-Dominated Heston PDE. SIAM J. Sci. Comput. Abhijit Ghosh, Chittaranjan Mishra
2021	J	`jnl`	Highly efficient parallel algorithms for solving the Bates PIDE for pricing options on a GPU. Appl. Math. Comput. Abhijit Ghosh, Chittaranjan Mishra
2017	—	`conf`	Regularized Stacked Auto-Encoder Based Pre-training for Generalization of Multi-layer Perceptron. TPNC Prasenjit Dey, Abhijit Ghosh, Tandra Pal
2000	Misc	`conf`	Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. VLSI Design Abhijit Ghosh, Ranga Vemuri
2000	—	`conf`	Methodology for hardware/software co-verification in C/C++ (short paper). ASP-DAC Luc Séméria, Abhijit Ghosh
2000	—	`conf`	YAML: A Tool for Hardware Design Visualization and Capture. ISSS Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh
1999	C	`conf`	Formal Verification of Synthesized Analog Designs. ICCD Abhijit Ghosh, Ranga Vemuri
1999	A	`conf`	Hardware Synthesis from C/C++. DATE Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao
1999	—	`conf`	Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. Great Lakes Symposium on VLSI Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri
1998	J	`jnl`	A Methodology for Feature Interaction Detection in the AIN 0.1 Framework. IEEE Trans. Software Eng. Fuchun Joseph Lin, Hong Liu, Abhijit Ghosh
1998	J	`jnl`	Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José Monteiro, Srinivas Devadas, Abhijit Ghosh
1997	J	`jnl`	Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White
1996	A	`conf`	An observability-based code coverage metric for functional simulation. ICCAD Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
1995	—	`conf`	Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
1995	J	`jnl`	Probabilistic manipulation of Boolean functions using free Boolean diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amelia Shen, Srinivas Devadas, Abhijit Ghosh
1994	A	`conf`	Precomputation-based sequential logic optimization for low power. ICCAD Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
1994	J	`jnl`	Precomputation-based sequential logic optimization for low power. IEEE Trans. Very Large Scale Integr. Syst. Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
1993	A	`conf`	Boolean factorization using multiple-valued minimization. ICCAD Stan Y. Liao, Srinivas Devadas, Abhijit Ghosh
1993	A	`conf`	Probabilistic construction and manipulation of free Boolean diagrams. ICCAD Amelia Shen, Srinivas Devadas, Abhijit Ghosh
1993	A	`conf`	Retiming sequential circuits for low power. ICCAD José Monteiro, Srinivas Devadas, Abhijit Ghosh
1993	J	`jnl`	Sequential test generation and synthesis for testability at the register-transfer and logic levels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1992	J	`jnl`	Boolean satisfiability and equivalence checking using general Binary Decision Diagrams. Integr. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas
1992	A*	`conf`	Estimation of Average Switching Activity in Combinational and Sequential Circuits. DAC Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob K. White
1992	J	`jnl`	Heuristic minimization of Boolean relations using testing techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1992	A	`conf`	On average power dissipation and random pattern testability of CMOS combinational logic networks. ICCAD Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer
1991	C	`conf`	Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. ICCD Pranav Ashar, Abhijit Ghosh, Srinivas Devadas
1991	Misc	`conf`	Recent progress in synthesis for testability. VTS Srinivas Devadas, Kurt Keutzer, Abhijit Ghosh
1991	J	`jnl`	Test generation and verification for highly sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	C	`conf`	Heuristic minimization of Boolean relations using testing techniques. ICCD Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	A	`conf`	Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	A*	`conf`	Sequential Test Generation at the Register-Transfer and Logic Levels. DAC Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	A	`conf`	Sequential logic synthesis for testability using register-transfer level descriptions. ITC Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	A*	`conf`	Verification of Interacting Sequential Circuits. DAC Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1989	A	`conf`	Test generation for highly sequential circuits. ICCAD Abhijit Ghosh, Srinivas Devadas, A. Richard Newton