Abhijit Dharchoudhury

16 papers A* 6A 5C 1Misc 2Journal 1

Year	Rank	Type	Title / Venue / Authors
1999	Misc	`conf`	A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury
1999	A*	`conf`	Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw
1999	—	`ch.`	Timing and Signal Integrity Analysis. The VLSI Handbook Steve M. Kang, Abhijit Dharchoudhury, David T. Blaauw, Stantanu Ganguly
1998	A	`conf`	CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
1998	A*	`conf`	Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
1998	A	`conf`	Emerging power management tools for processor design. ISLPED David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
1998	A*	`conf`	Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw
1997	A	`conf`	Library-less synthesis for static CMOS combinational logic circuits. ICCAD Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
1997	C	`conf`	Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning
1996	A*	`conf`	iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. DAC Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang
1995	J	`jnl`	Worst-case analysis and optimization of VLSI circuit performances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhijit Dharchoudhury, Sung-Mo Kang
1994	A	`conf`	Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. ICCAD Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee
1994	A	`conf`	Fast timing simulation of transient faults in digital circuits. ICCAD Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel
1993	A*	`conf`	Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. DAC Abhijit Dharchoudhury, Sung-Mo Kang
1992	A*	`conf`	An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. DAC Abhijit Dharchoudhury, Sung-Mo Kang
1992	Misc	`conf`	Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis. VLSI Design Abhijit Dharchoudhury, S. M. Kang