Abdulkadir Utku Diril

18 papers A 2C 2Misc 3Journal 6Unranked 4
YearRankTypeTitle / Venue / Authors
2008 J jnl
Performance-Optimized Design for Parametric Reliability.
J. Electron. Test.
Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
2007 J jnl
Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption.
J. Low Power Electron.
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
2007 Misc conf
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.
VLSI Design
Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril
2007 J jnl
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
CoRR
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
2006 — conf
Adaptive Design for Performance-Optimized Robustness.
DFT
Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
2006 J jnl
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.
IEEE Trans. Very Large Scale Integr. Syst.
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
2005 — —
Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic.
Abdulkadir Utku Diril
2005 Misc conf
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.
VTS
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005 Misc conf
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages.
VLSI Design
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005 J jnl
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.
IEEE Trans. Very Large Scale Integr. Syst.
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005 C conf
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.
IOLTS
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra
2005 — conf
Low-power domino circuits using NMOS pull-up on off-critical paths.
ASP-DAC
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005 J jnl
Pseudo Dual Supply Voltage Domino Logic Design.
J. Low Power Electron.
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005 A conf
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits.
DATE
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
2004 — conf
Low-power dual V
SBCCI
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
2004 C conf
Sizing CMOS Circuits for Increased Transient Error Tolerance.
IOLTS
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
2003 A conf
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level.
ICCAD
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee
2003 — conf
An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs.
ISVLSI
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee