Abdolah Amirany

25 papers A* 1Misc 1Journal 20Unranked 3

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A new method for securing binary deep neural networks against model replication attacks using magnetic tunnel junctions. Int. J. Inf. Sec. Mohammad Hadi Rezayati, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
2025	J	`jnl`	BAM-Net: Hardware Friendly Associative Memory Using Binary Dominant Weights and NAND Logic. IEEE Access Abdolah Amirany, Belal Jahannia, Abdulaziz S. Bazammul, Hamed Dalir, Elham Heidari
2025	J	`jnl`	Balancing precision and efficiency: an approximate multiplier with built-in error compensation for error-resilient applications. J. Supercomput. Ladan Sayadi, Abdolah Amirany, Mohammad Hossein Moaiyeri, Somayeh Timarchi
2025	J	`jnl`	DaLAMED: A Clock-Frequency and Data-Lifetime-Aware Methodology for Energy-Efficient Memory Design in Edge Devices. IEEE Access Belal Jahannia, Abdolah Amirany, Elham Heidari, Hamed Dalir
2025	J	`jnl`	Efficient and High Accuracy Approximate Multiplier Design Approach for AI Application. Circuits Syst. Signal Process. Faraz Baraati, Milad Tanavardi Nasab, Abdolah Amirany, Kian Jafari, Reza Ghaderi
2025	J	`jnl`	Immunization of binarized deep neural networks against model replication attacks based on stochastic magnetoresistive RAMs. Int. J. Mach. Learn. Cybern. Mohammad Hadi Rezayati, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
2025	A*	`conf`	QoS-Efficient Serving of Multiple Mixture-of-Expert LLMs Using Partial Runtime Reconfiguration. ICML Hamid Reza Imani, Jiaxin Peng, Peiman Mohseni, Abdolah Amirany, Tarek A. El-Ghazawi
2025	J	`jnl`	QoS-Efficient Serving of Multiple Mixture-of-Expert LLMs Using Partial Runtime Reconfiguration. CoRR Hamid Reza Imani, Jiaxin Peng, Peiman Mohseni, Abdolah Amirany, Tarek A. El-Ghazawi
2025	J	`jnl`	Synergizing spintronics and quaternary logic: a hardware accelerator for neural networks with optimized quantization algorithm. J. Supercomput. Motahareh BahmanAbadi, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
2024	J	`jnl`	A New Paradigm for Immunization of Deep Neural Networks Against Replication Attacks Based on Spintronics. IEEE Trans. Circuits Syst. II Express Briefs Mohammad Hadi Rezayati, Mohammad Hossein Moaiyeri, Abdolah Amirany, Kian Jafari
2024	J	`jnl`	Low-Cost and Variation-Aware Spintronic Ternary Random Number Generator. Circuits Syst. Signal Process. Fatemeh Khodayari, Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri
2024	—	`conf`	Mixture of Experts with Mixture of Precisions for Tuning Quality of Service. ICRC Hamid Reza Imani, Abdolah Amirany, Tarek A. El-Ghazawi
2024	J	`jnl`	Mixture of Experts with Mixture of Precisions for Tuning Quality of Service. CoRR Hamid Reza Imani, Abdolah Amirany, Tarek A. El-Ghazawi
2024	J	`jnl`	On the Layout-Oriented Investigation of Power Attack Hardness of Spintronic-Based Logic Circuits. Circuits Syst. Signal Process. Pegah Iranfar, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
2024	J	`jnl`	Protecting the Intellectual Property of Binary Deep Neural Networks With Efficient Spintronic-Based Hardware Obfuscation. IEEE Trans. Circuits Syst. I Regul. Pap. Alireza Mohseni, Mohammad Hossein Moaiyeri, Abdolah Amirany, Mohammad Hadi Rezayati
2024	J	`jnl`	RLFL: A Reinforcement Learning Aggregation Approach for Hybrid Federated Learning Systems Using Full and Ternary Precision. IEEE J. Emerg. Sel. Topics Circuits Syst. Hamid Reza Imani, Jeff Anderson, Samuel Farid, Abdolah Amirany, Tarek A. El-Ghazawi
2024	J	`jnl`	TPCSA-MRAM: Ternary Precharge Sense Amplifier-Based MRAM. IEEE Access Mohammad Mahdi Mazaheri, Abdolah Amirany, Mohammad Hossein Moaiyeri
2023	J	`jnl`	A Fast and Light Fingerprint-Matching Model Based on Deep Learning Approaches. J. Signal Process. Syst. Hamid Shafaghi, Meysam Kiani, Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri
2023	J	`jnl`	A high-capacity and nonvolatile spintronic associative memory hardware accelerator. IET Circuits Devices Syst. Mahan Rezaei, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
2023	J	`jnl`	High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator. IEEE Trans. Emerg. Top. Comput. Milad Tanavardi Nasab, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
2022	J	`jnl`	Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons. IEEE Trans. Emerg. Top. Comput. Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
2021	J	`jnl`	High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register. IEEE Trans. Very Large Scale Integr. Syst. Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri
2021	—	`conf`	MTMR-SNQM: Multi-Tunnel Magnetoresistance Spintronic Non-volatile Quaternary Memory. ISMVL Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
2021	Misc	`conf`	Stochastic Spintronic Neuron with Application to Image Binarization. CSICC Abdolah Amirany, Masoud Meghdadi, Mohammad Hossein Moaiyeri, Kian Jafari
2020	—	`conf`	Low-Cost Implementation of Bilinear and Bicubic Image Interpolation for Real-Time Image Super-Resolution. GHTC Donya Khaledyan, Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri, Abolfazl Zargari Khuzani, Najmeh Mashhadi