Abdelkarim Cherkaoui

20 papers A 3Journal 3Unranked 14
YearRankTypeTitle / Venue / Authors
2021 J jnl
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits.
IEEE Des. Test
Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet
2021 — conf
An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study.
ICECS
Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet
2020 — conf
A Self-Timed Ring based PUF.
ASYNC
Grégoire Gimenez, Abdelkarim Cherkaoui, Laurent Fesquet
2018 J jnl
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cédric Marchand, Lilian Bossuet, Ugo Mureddu, Nathalie Bochard, Abdelkarim Cherkaoui, Viktor Fischer
2018 — conf
Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring.
DCIS
Oussama Elissati, Assia El-Hadbi, Abdelkarim Cherkaoui, Sébastien Rieubon, Laurent Fesquet
2018 — conf
Static Timing Analysis of Asynchronous Bundled-Data Circuits.
ASYNC
Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet
2018 — conf
Subthreshold logic for low-area and energy efficient true random number generator.
COOL CHIPS
Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal
2017 — conf
A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines.
ASYNC
Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet
2017 — conf
CAR: On the highway towards de-synchronization.
ICECS
François Bertrand, Abdelkarim Cherkaoui, Jean Simatic, Anthony Maure, Laurent Fesquet
2017 — conf
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept.
NEWCAS
Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet
2017 — conf
Self-timed Ring based True Random Number Generator: Threat model and countermeasures.
IVSW
Gregoire Gimenez, Abdelkarim Cherkaoui, Raphael Frisch, Laurent Fesquet
2016 — conf
Design and Characterization of the TERO-PUF on SRAM FPGAs.
ISVLSI
Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui
2016 J jnl
Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators.
IEEE Trans. Inf. Forensics Secur.
Abdelkarim Cherkaoui, Lilian Bossuet, Cédric Marchand
2016 A conf
Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only).
FPGA
Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui
2016 — conf
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines.
SBCCI
Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet
2014 — conf
New paradigms for access control in constrained environments.
ReCoSoC
Abdelkarim Cherkaoui, Lilian Bossuet, Ludwig Seitz, Göran Selander, Ravishankar Borgaonkar
2014 — conf
Self-timed rings as low-phase noise programmable oscillators.
NEWCAS
Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati
2013 — conf
A Self-Timed Ring Based True Random Number Generator.
ASYNC
Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet
2013 A conf
A Very High Speed True Random Number Generator with Entropy Assessment.
CHES
Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert
2012 A conf
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs.
DATE
Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet