Abdel Ejnioui

42 papers A 1C 3Misc 4Journal 9Unranked 25
YearRankTypeTitle / Venue / Authors
2015 — conf
Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics.
NATW
Rawad N. Al-Haddad, Rashad S. Oreifej, Ramtin Zand, Abdel Ejnioui, Ronald F. DeMara
2013 J jnl
A stochastic approach for evaluating quality of service in wireless cellular networks.
Int. J. Wirel. Mob. Comput.
Abdel Ejnioui, Carlos E. Otero, Ivica Kostanic
2013 — conf
A support vector machine for terrain classification in on-demand deployments of wireless sensor networks.
SysCon
Rana Haber, Adrian M. Peter, Carlos E. Otero, Ivica Kostanic, Abdel Ejnioui
2013 — conf
Engineering graphic user interfaces with protected content.
SysCon
Abdel Ejnioui, Carlos E. Otero, Abrar A. Qureshi
2013 — conf
Formalizing the design of embedded software using sequence diagrams and abstract state machines.
RIIT
Abdel Ejnioui, Carlos E. Otero, Abrar A. Qureshi
2013 J jnl
Prioritisation of software requirements using grey relational analysis.
Int. J. Comput. Appl. Technol.
Abdel Ejnioui, Carlos E. Otero, Luis Daniel Otero
2013 — conf
System analysis methods in emergency systems.
SysCon
Jeffrey A. McDougall, Luis Daniel Otero, Juan Avendano, Abdel Ejnioui
2012 — conf
A simulation-based fuzzy multi-attribute decision making for prioritizing software requirements.
RIIT
Abdel Ejnioui, Carlos E. Otero, Luis Daniel Otero
2011 J jnl
Evaluation of Information Security Controls in Organizations by Grey Relational Analysis.
Int. J. Dependable Trust. Inf. Syst.
Angel R. Otero, Abdel Ejnioui, Carlos E. Otero, Gurvirender Tejay
2009 — conf
Runtime Adaptation in Reconfigurable System-on-Chips.
ICPP Workshops
Abdel Ejnioui
2008 — conf
A Parallel Array to Accelerate GFA Modeling in Video Coding.
ERSA
Abdel Ejnioui, Paul Bao
2008 C conf
A parallel architecture for GFA modeling in video coding.
CIT
Abdel Ejnioui, Paul Bao
2007 — conf
FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline.
ISVLSI
Abdel Ejnioui
2007 — conf
Hardware Acceleration of the Generalized Finite Automata Algorithm.
CDES
Abdel Ejnioui, Paul Bao
2007 — conf
Hardware Architectures for the Generalized Finite Automata Algorithm.
ICECS
Abdel Ejnioui, Paul Bao
2007 — conf
Prototyping of a Two-Phase Micropipeline on FPGAs.
ERSA
Abdel Ejnioui
2007 J jnl
Role of the C language in current computing curricula part 1: survey analysis.
J. Comput. Sci. Coll.
Alessio Gaspar, Naomi R. Boyer, Abdel Ejnioui
2007 J jnl
Tiered Algorithm for Distributed Process Quiescence and Termination Detection.
IEEE Trans. Parallel Distributed Syst.
Ronald F. DeMara, Yili Tseng, Abdel Ejnioui
2006 Misc conf
Clockless Pipelining for Coarse Grain Datapaths.
VLSI Design
Abdelhalim Alsharqawi, Abdel Ejnioui
2006 — conf
Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study.
ERSA
Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler
2006 — conf
Pipelining of double precision floating point division and square root operations.
ACM Southeast Regional Conference
Anuja Jayraj Thakkar, Abdel Ejnioui
2006 — conf
Synthesis of Pipelined SRSL Circuits.
ISVLSI
Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui
2005 — conf
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices.
ERSA
Abdel Ejnioui, Ronald F. DeMara
2005 — conf
Pipeline synthesis of SRSL circuits.
ICECS
Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui
2005 — conf
SRSL pipelining of coarse-grain datapaths.
ICECS
Abdelhalim Alsharqawi, Abdel Ejnioui
2005 — conf
Synthesis of Self-Resetting Stage Logic Pipelines.
ISVLSI
Abdelhalim Alsharqawi, Abdel Ejnioui
2004 — conf
A Reconfigurable Memory Management Core for Java Applications.
ISVLSI
Abdel Ejnioui, Abdelkader Rhiati
2004 — conf
Control and Data Flow Graph Extraction for High-Level Synthesis.
ISVLSI
Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui
2004 — conf
Pipeline Design Based on Self-Resetting Stage Logic.
ISVLSI
Abdel Ejnioui, Abdelhalim Alsharqawi
2004 C conf
Pipeline-Level Control of Self-Resetting Pipelines.
DSD
Abdel Ejnioui, Abdelhalim Alsharqawi
2004 — conf
Self-resetting stage logic pipelines.
ACM Great Lakes Symposium on VLSI
Abdel Ejnioui, Abdelhalim Alsharqawi
2003 J jnl
Multiterminal net routing for partial crossbar-based multi-FPGA systems.
IEEE Trans. Very Large Scale Integr. Syst.
Abdel Ejnioui, N. Ranganathan
2003 J jnl
Routing on field-programmable switch matrices.
IEEE Trans. Very Large Scale Integr. Syst.
Abdel Ejnioui, N. Ranganathan
2003 — conf
Supply Voltage Scalable System Design Using Self-Timed Circuits.
ISVLSI
W. Kuang, J. S. Yuan, Abdel Ejnioui
2002 — conf
A VLSI Architecture for Object Recognition Using Tree Matching.
ASAP
K. Sitaraman, N. Ranganathan, Abdel Ejnioui
2001 J jnl
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.
IEEE Trans. Very Large Scale Integr. Syst.
Abdel Ejnioui, N. Ranganathan
2000 Misc conf
Design Partitioning on Single-Chip Emulation Systems.
VLSI Design
Abdel Ejnioui, N. Ranganathan
2000 Misc conf
Routing on Switch Matrix Multi-FPGA Systems.
VLSI Design
Abdel Ejnioui, N. Ranganathan
1999 J jnl
A tree-matching chip.
IEEE Trans. Very Large Scale Integr. Syst.
Vamsi Krishna, N. Ranganathan, Abdel Ejnioui
1999 A conf
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems.
FPGA
Abdel Ejnioui, N. Ranganathan
1996 Misc conf
A tree matching chip.
VLSI Design
Vamsi Krishna, Abdel Ejnioui, N. Ranganathan
1995 C conf
Systolic algorithms for tree pattern matching.
ICCD
Abdel Ejnioui, N. Ranganathan