Abdallah Cheikh

29 papers B 1Journal 10Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Configurable Hardware Acceleration for Hyperdimensional Computing Extension on RISC-V. IEEE Trans. Computers Rocco Martino, Marco Angioli, Antonello Rosato, Marcello Barbirotta, Abdallah Cheikh, Mauro Olivieri
2025	J	`jnl`	Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. CoRR Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2025	J	`jnl`	Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. ACM Trans. Embed. Comput. Syst. Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2025	—	`conf`	Re-Architecting RISC-V: A 64-Bit Take on Interleaved Multi-threading. ApplePies Andrea Marcelli, Marco Pisani, Rocco Martino, Abdallah Cheikh, Francesco Menichelli, Mauro Olivieri
2024	J	`jnl`	A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection. IEEE Access Francesco Vigli, Marcello Barbirotta, Abdallah Cheikh, Francesco Menichelli, Antonio Mastrandrea, Mauro Olivieri
2024	B	`conf`	AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs. IJCNN Marco Angioli, Saeid Jamili, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Antonello Rosato, Mauro Olivieri
2024	—	`conf`	Alternative Implementations of Error Correcting Codes in Register Files of a RISC-V Safety Critical Processor. ApplePies Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Francesco Menichelli, Mauro Olivieri
2024	J	`jnl`	Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. IEEE Trans. Computers Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
2024	—	`conf`	Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation. DFT Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri
2024	J	`jnl`	Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. IEEE Access Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
2024	—	`conf`	Exploring Variable Latency Dividers in Vector Hardware Accelerators. PRIME Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri
2024	—	`conf`	Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor. DFT Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri
2023	—	`conf`	A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. ApplePies Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
2023	—	`conf`	Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. ApplePies Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri
2023	—	`conf`	Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. ApplePies Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri
2022	—	`conf`	Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. PRIME Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2022	—	`conf`	Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. ApplePies Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
2022	J	`jnl`	Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. IEEE Access Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2022	—	`conf`	Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ApplePies Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
2021	—	`conf`	A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. DFT Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri
2021	J	`jnl`	Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. IEEE Micro Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
2020	—	`—`	Energy-efficient digital electronic systems design for edge-computing applications, through innovative RISC-V compliant processors. Abdallah Cheikh
2020	—	`conf`	Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. DFT Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri
2020	J	`jnl`	Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. CoRR Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
2019	—	`conf`	A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. ApplePies Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2019	—	`conf`	Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. ApplePies Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2017	—	`conf`	Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. NGCAS Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli
2017	—	`conf`	The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. ApplePies Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2017	J	`jnl`	The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. CoRR Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri