Abanob Shehata

11 papers Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 52 Gb/s 8.9-dBm EIRP 300-GHz-Band Amplifier-Last Outphasing Transmitter With Path Mismatch Calibration in 65-nm CMOS.
IEEE J. Solid State Circuits
Chun Wang, Olivia Angel Yong, Hans Herdian, Wenqian Wang, Abanob Shehata, Carrel da Gomez, Chenxin Liu, Yudai Yamazaki, Kazuaki Kunihiro, Hiroyuki Sakai, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada
2025 J jnl
A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112-170 GHz for 6G Transceivers.
IEEE Solid State Circuits Lett.
Chenxin Liu, Yudai Yamazaki, Anyi Tian, Chun Wang, Hans Herdian, Abanob Shehata, Han Nie, Minzhe Tang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2025 J jnl
A Compact D-Band Phase Shifter With 0.1-Degree Phase Resolution and Ultra-Low Phase Error in 65-nm CMOS.
IEEE J. Solid State Circuits
Takaya Uchino, Yudai Yamazaki, Anyi Tian, Chenxin Liu, Sunghwan Park, Abanob Shehata, Sena Kato, Takumi Kojima, Haruto Tanaka, Masayuki Kikuchi, Jill C. Mayeda, Ryuji Kinugawa, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2024 — conf
24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS.
ISSCC
Chun Wang, Hans Herdian, Wenbin Zheng, Chenxin Liu, Jill C. Mayeda, Yuxuan Liu, Olivia Angel Yong, Wenqian Wang, Yuncheng Zhang, Carrel da Gomez, Abanob Shehata, Sena Kato, Ibrahim Abdo, Teruo Jyo, Hiroshi Hamada, Hiroyuki Takahashi, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2024 — conf
35-60GHz Switchless IF Bi-Directional Amplifier Using 65nm CMOS for 300GHz-Band Transceivers.
A-SSCC
Abanob Shehata, Hans Herdian, Chun Wang, Chenxin Liu, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2024 — conf
A Compact D-Band Phase Shifter with 0.1-degree Phase Resolution and 0.8-degree RMS Phase Error in 65 nm CMOS.
A-SSCC
Takaya Uchino, Yudai Yamazaki, Sunghwan Park, Chenxin Liu, Anyi Tian, Abanob Shehata, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2024 J jnl
A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression.
IEEE J. Solid State Circuits
Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Jill C. Mayeda, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang, Jian Pang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2023 — conf
A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression.
VLSI Technology and Circuits
Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang, Jian Pang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2022 J jnl
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.
IEEE J. Solid State Circuits
Simone Mattia Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
2021 — conf
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.
ISSCC
Alessio Santiccioli, Mario Mercandelli, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
2021 — conf
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.
ISSCC
Mario Mercandelli, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata, Francesco Tesolin, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea Leonardo Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino