Aart J. de Geus

18 papers A* 7A 1C 1Journal 7Unranked 2
YearRankTypeTitle / Venue / Authors
2014 J jnl
The Greatest "Tech-Onomic Push-Pull" in Human History.
IEEE Des. Test
Aart J. de Geus
2007 J jnl
A. Richard Newton: Technologist with a Mission.
IEEE Des. Test Comput.
Aart J. de Geus
2007 A* conf
Megatrends and EDA 2017.
DAC
Francine Bacchini, Gregory S. Spirakis, Juan Antonio Carballo, Kurt Keutzer, Aart J. de Geus, Fu-Chieh Hsu, Kazu Yamada
2005 A* conf
Differentiate and deliver: leveraging your partners.
DAC
Jay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy
2004 A* conf
EDA: this is serious business.
DAC
Robert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines
2002 — conf
Electronic Industry on Fire: How to Survive and Thrive.
ASP-DAC/VLSI Design
Aart J. de Geus
2000 — conf
Slap it Together and Ship it!
ISQED
Aart J. de Geus
1994 A* conf
Executive Perspective and Vision of the Future of EDA (Panel).
DAC
Joseph B. Costello, Walden C. Rhines, Aart J. de Geus, Alain Hanover, Doug Fairbairn, Rick Carlson, Ronald Collett
1994 A conf
Test: The New Value-Added Field.
ITC
Aart J. de Geus
1992 C conf
High Level Design: A Design Vision for the 90's.
ICCD
Aart J. de Geus
1992 J jnl
VHDL: Toward a Unified View of Design.
IEEE Des. Test Comput.
Allen Dewey, Aart J. de Geus
1987 J jnl
Testability-Driven Random Test-Pattern Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory
1986 J jnl
Computer-Aided-Design Research at the GE Microelectronics Center.
IEEE Des. Test
David Hightower, Aart J. de Geus, Patrick Fasang, Robert Griffin, Gary Leive
1986 A* conf
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference.
DAC
Aart J. de Geus
1986 A* conf
SOCRATES: a system for automatically synthesizing and optimizing combinational logic.
DAC
David Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel
1986 J jnl
Synthesis and Optimization of Multilevel Logic under Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel
1985 J jnl
A Rule-Based System for Optimizing Combinational Logic.
IEEE Des. Test
Aart J. de Geus, William W. Cohen
1984 A* conf
IDA: Interconnect delay analysis for integrated circuits.
DAC
Aart J. de Geus, J. B. Reed, M. Rekhson, G. Wikle