A. Richard Newton

113 papers A* 28A 21C 8Misc 1Journal 39Unranked 15

Year	Rank	Type	Title / Venue / Authors
2006	—	`conf`	Fast Boolean Matching with Don't Cares. ISQED Zile Wei, Donald Chai, A. Richard Newton, Andreas Kuehlmann
2005	J	`jnl`	Recognition and beautification of multi-stroke symbols in digital ink. Comput. Graph. Heloise Hwawen Hse, A. Richard Newton
2004	—	`conf`	Digital Image Restoration by Exposure-Splitting and Registration. ICPR (4) Zile Wei, Yu Cao, A. Richard Newton
2004	Misc	`conf`	Great works for the 21st century: a critical role for the modern research university. EMSOFT A. Richard Newton
2004	—	`conf`	Recognition and Beautification of Multi-Stroke Symbols in Digital Ink. AAAI Technical Report (6) Heloise Hwawen Hse, A. Richard Newton
2004	A	`conf`	Robust sketched symbol fragmentation using templates. IUI Heloise Hwawen Hse, Michael Shilman, A. Richard Newton
2004	—	`conf`	Sketched Symbol Recognition using Zernike Moments. ICPR (1) Heloise Hwawen Hse, A. Richard Newton
2002	C	`conf`	From ASIC to ASIP: The Next Design Discontinuity. ICCD Kurt Keutzer, Sharad Malik, A. Richard Newton
2001	J	`jnl`	Learning as applied to stochastic optimization for standard-cellplacement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lixin Su, Wray L. Buntine, A. Richard Newton, Bradley S. Peters
2001	J	`jnl`	Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, A. Richard Newton, Lawrence T. Pileggi, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
2000	A*	`conf`	Embedded systems design in the new millennium (panel session). DAC A. Richard Newton, Walden C. Rhines, Sünke Mehrgardt, Henry Samueli, Tudor Brown
2000	J	`jnl`	Integration of retiming with architectural floorplanning. Integr. Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton
2000	A*	`conf`	Predicting performance potential of modern DSPs. DAC Naji Ghazal, A. Richard Newton, Jan M. Rabaey
2000	—	`conf`	Retargetable estimation scheme for DSP architecture selection. ASP-DAC Naji Ghazal, A. Richard Newton, Jan M. Rabaey
2000	J	`jnl`	System-level design: orthogonalization of concerns andplatform-based design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kurt Keutzer, A. Richard Newton, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
1999	A*	`conf`	Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. DAC Abdallah Tabbara, Robert K. Brayton, A. Richard Newton
1999	C	`conf`	The MARCO/DARPA Gigascale Silicon Research Center. ICCD Kurt Keutzer, A. Richard Newton
1998	A*	`conf`	Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement. DAC James Shin Young, Josh MacDonald, Michael Shilman, Abdallah Tabbara, Paul N. Hilfinger, A. Richard Newton
1998	C	`conf`	Learning as applied to stochastic optimization for standard cell placement. ICCD Lixin Su, Wray L. Buntine, A. Richard Newton, Bradley S. Peters
1998	A*	`conf`	Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). DAC A. Richard Newton
1998	A*	`conf`	WELD - An Environment for Web-based Electronic Design. DAC Francis L. Chan, Mark D. Spiller, A. Richard Newton
1997	A	`conf`	Adaptive methods for netlist partitioning. ICCAD Wray L. Buntine, Lixin Su, A. Richard Newton, Andrew Mayer
1997	A	`conf`	EDA and the network. ICCAD Mark D. Spiller, A. Richard Newton
1997	A	`conf`	Engineering change for power optimization using global sensitivity and synthesis flexibility. ISLPED Premal Buch, Christopher K. Lennard, A. Richard Newton
1997	J	`jnl`	Formal methods into practice: case studies in the application of the B method. IEE Proc. Softw. Eng. Juan Bicarregui, D. L. Clutterbuck, Gavin R. Finnie, Howard P. Haughton, Kevin Lano, H. Lesan, D. W. R. M. Marsh, B. M. Matthews, Michael R. Moulding, A. Richard Newton, Brian Ritchie, T. G. A. Rushton, P. N. Scharbach
1997	A	`conf`	Logic synthesis for large pass transistor circuits. ICCAD Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1997	—	`conf`	The future of logic synthesis and physical design in deep-submicron process geometries. ISPD Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy
1996	A	`conf`	Logic synthesis using power-sensitive don't care sets. ISLPED Christopher K. Lennard, Premal Buch, A. Richard Newton
1996	J	`jnl`	On estimation accuracy for guiding low-power resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Christopher K. Lennard, A. Richard Newton
1996	—	`conf`	The maximal VHDL subset with a cycle-level abstraction. EURO-DAC Wendell C. Baker, A. Richard Newton
1995	—	`conf`	An estimation technique to guide low power resynthesis algorithms. ISLPD Christopher K. Lennard, A. Richard Newton
1994	J	`jnl`	Algorithms for the transient simulation of lossy interconnect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson
1994	—	`book`	Mixed-mode simulation and analog multilevel simulation. Resve A. Saleh, Shyh-Jye Jou, A. Richard Newton
1994	A	`conf`	TOBAC: A Test Case Browser for Testing Object-Oriented Software. ISSTA Ernst Siepmann, A. Richard Newton
1993	J	`jnl`	Sequential test generation and synthesis for testability at the register-transfer and logic levels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1993	J	`jnl`	Two-Level Minimization of Multivalued Functions with Large Offsets. IEEE Trans. Computers Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1992	—	`conf`	An exact analytic technique for simulating uniform RC lines. EURO-DAC Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson
1992	—	`conf`	Experiments on the synthesis and testability of non-scan finite state machines. EURO-DAC Michael Pabst, Tiziano Villa, A. Richard Newton
1992	J	`jnl`	Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Takayasu Sakurai, Bill Lin, A. Richard Newton
1992	J	`jnl`	Heuristic minimization of Boolean relations using testing techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1992	A*	`conf`	Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time. DAC Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson
1991	A	`conf`	A Cell-Replicating Approach to Minicut-Based Circuit Partitioning. ICCAD Chuck Kring, A. Richard Newton
1991	A	`conf`	An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy Interconnect Simulation. ICCAD Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson
1991	J	`jnl`	An efficient verifier for finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seung Ho Hwang, A. Richard Newton
1991	J	`jnl`	Delay analysis of series-connected MOSFET circuits. IEEE J. Solid State Circuits Takayasu Sakurai, A. Richard Newton
1991	—	`conf`	Exact Redundant State Registers Removal Based on Binary Decision Diagrams. VLSI Bill Lin, A. Richard Newton
1991	J	`jnl`	Exact algorithms for output encoding, state assignment, and four-level Boolean minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, A. Richard Newton
1991	A*	`conf`	Framework Standards: How Important are They? (Panel Abstract). DAC A. Richard Newton
1991	—	`conf`	Has CAD for VLSI Reached a Dead End? VLSI A. Richard Newton
1991	C	`conf`	Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams. ICCD Bill Lin, A. Richard Newton
1991	J	`jnl`	Irredundant interacting sequential machines via optimal logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pranav Ashar, Srinivas Devadas, A. Richard Newton
1991	J	`jnl`	MUSE: a multilevel symbolic encoding algorithm for state assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xuejun Du, Gary D. Hachtel, Bill Lin, A. Richard Newton
1991	J	`jnl`	Optimum and heuristic algorithms for an approach to finite state machine decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pranav Ashar, Srinivas Devadas, A. Richard Newton
1991	A*	`ed.`	Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991. DAC A. Richard Newton
1991	J	`jnl`	Reduced offsets for minimization of binary-valued functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1991	J	`jnl`	Test generation and verification for highly sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	A*	`conf`	A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. DAC Pranav Ashar, Srinivas Devadas, A. Richard Newton
1990	J	`jnl`	A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bill Lin, A. Richard Newton
1990	A*	`conf`	Abstract Data Types and High-Level Synthesis. DAC Gregory S. Whitcomb, A. Richard Newton
1990	J	`jnl`	Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. Solid State Circuits Takayasu Sakurai, A. Richard Newton
1990	A*	`conf`	An Empirical Evaluation of Two Memory-Efficient Directory Methods. ISCA Brian W. O'Krafka, A. Richard Newton
1990	A*	`conf`	Design Management Based on Design Traces. DAC Andrea Casotto, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1990	A	`conf`	Don't Care Minimization of Multi-Level Sequential Logic Networks. ICCAD Bill Lin, Hervé J. Touati, A. Richard Newton
1990	C	`conf`	Heuristic minimization of Boolean relations using testing techniques. ICCD Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	A	`conf`	Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	J	`jnl`	Irredundant sequential machines via optimal logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1990	A*	`conf`	Reduced Offsets for Two-Level Multi-Valued Logic Minimization. DAC Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1990	J	`jnl`	Redundancies and don't cares in sequential logic synthesis. J. Electron. Test. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
1990	A*	`conf`	Sequential Test Generation at the Register-Transfer and Logic Levels. DAC Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	A	`conf`	Sequential logic synthesis for testability using register-transfer level descriptions. ITC Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	A*	`conf`	Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract). DAC A. Richard Newton
1990	C	`conf`	Testability driven synthesis of interacting finite state machines. ICCD Pranav Ashar, Srinivas Devadas, A. Richard Newton
1990	A*	`conf`	Verification of Interacting Sequential Circuits. DAC Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1989	C	`conf`	A generalized approach to the constrained cubical embedding problem. ICCD Bill Lin, A. Richard Newton
1989	J	`jnl`	A synthesis and optimization procedure for fully and easily testable sequential machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1989	J	`jnl`	Algorithms for hardware allocation in data path synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, A. Richard Newton
1989	J	`jnl`	Boolean decomposition in multilevel logic optimization. IEEE J. Solid State Circuits Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1989	J	`jnl`	Decomposition and factorization of sequential finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, A. Richard Newton
1989	—	`conf`	Easily testable PLA-based finite state machines. FTCS Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
1989	J	`jnl`	Electrical-logic simulation and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Young Hwan Kim, Seung Ho Hwang, A. Richard Newton
1989	A	`conf`	Optimum and heuristic algorithms for finite state machine decomposition and partitioning. ICCAD Pranav Ashar, Srinivas Devadas, A. Richard Newton
1989	A	`conf`	Redundancies and Don't Cares in Sequential Logic Synthesis. ITC Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
1989	A	`conf`	SLIP: a software environment for system level interactive partitioning. ICCAD Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton
1989	A	`conf`	Test generation for highly sequential circuits. ICCAD Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1989	J	`jnl`	The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Resve A. Saleh, A. Richard Newton
1988	A	`conf`	A modified approach to two-level logic minimization. ICCAD Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1988	A	`conf`	An Incomplete Scan Design Approach to Test Generation for Sequential Machines. ITC Hi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli
1988	A	`conf`	Boolean decomposition in multi-level logic optimization. ICCAD Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1988	C	`conf`	Critic: a knowledge-based program for critiquing circuit designs. ICCD Rick L. Spickelmier, A. Richard Newton
1988	A	`conf`	Decomposition and factorization of sequential finite state machines. ICCAD Srinivas Devadas, A. Richard Newton
1988	J	`jnl`	MUSTANG: state assignment of finite state machines targeting multilevel logic implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1988	J	`jnl`	On the verification of sequential machines at differing levels of abstraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
1988	A*	`ed.`	Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988. DAC Dennis W. Shaklee, A. Richard Newton
1988	A	`conf`	Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines. ITC Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1988	J	`jnl`	Test generation for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1988	A*	`conf`	Twenty-Five Years of Electronic Design Automation. DAC A. Richard Newton
1987	A*	`conf`	KAHLUA: A Hierarchical Circuit Disassembler. DAC Bill Lin, A. Richard Newton
1987	A*	`conf`	On the Verification of Sequential Machines at Differing Levels of Abstraction. DAC Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
1987	J	`jnl`	Topological Optimization of Multiple-Level Array Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, A. Richard Newton
1986	A*	`conf`	An accuration delay modeling technique for switch-level timing verification. DAC Seung Ho Hwang, Young Hwan Kim, A. Richard Newton
1986	A*	`conf`	An empirical analysis of the performance of a multiprocessor-based circuit simulator. DAC George K. Jacob, A. Richard Newton, Donald O. Pederson
1986	J	`jnl`	Computer-Aided Design for VLSI Circuits. Computer A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1986	A*	`conf`	GENIE: a generalized array optimizer for VLSI synthesis. DAC Srinivas Devadas, A. Richard Newton
1986	—	`conf`	Highlights of VLSI Research at Berkeley. FJCC Carlo H. Séquin, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1985	J	`jnl`	Design Aids for VLSI: A Perspective Revisited. IEEE Des. Test A. Richard Newton, Donald O. Pederson, Alberto L. Sangiovanni-Vincentelli
1984	A*	`conf`	A multiprocessor implementation of relaxation-based electrical circuit simulation. DAC Jeffrey T. Deutsch, A. Richard Newton
1984	J	`jnl`	Relaxation-Based Electrical Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1983	J	`jnl`	Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Giovanni De Micheli, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1982	A*	`conf`	A symbolic design system for integrated circuits. DAC Kenneth H. Keller, A. Richard Newton, S. Ellis
1982	J	`jnl`	An Algorithm for Optimal PLA Folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1982	—	`conf`	KIC2: A Low-Cost, Interactive Editor for Integrated Circuit Design. COMPCON Kenneth H. Keller, A. Richard Newton
1982	A*	`conf`	Techniques for programmable logic array folding. DAC Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1980	A*	`conf`	The VLSI design challenge of the 80's (Position Statement). DAC A. Richard Newton